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Redirected from: complementary field-effect transistor
Definition: CFET
(Complementary Field-Effect Transistor) The next-generation of field-effect transistors following GAAFET. Almost all chip circuits are built using CMOS logic, which pairs one n-type transistor (nFET) with a p-type transistor (pFET). However, a horizontal separator between the two takes up space. See GAAFET.
Increased Density through Stacking
Emerging in the late 2020s, CFETs will stack the CMOS transistor pairs on top of each other, automatically doubling the density of chips. Estimates are that the first CFET chips will contain approximately 150 to 200 million transistors per square millimeter, up from the 100 million or so today.
Even More Layers
A Half Billion Transistors on a Pinhead!
Today, a chip can contain more than 100 million transistors per square millimeter, about the same area as the head of a pin. When 3D architecture like the layers example above is employed and fully matured for complete circuits, the number of transistors should triple, quadruple and even quintuple. That means a half billion transistors per square millimeter are possible within the next decade! Stay tuned! See Cerebras AI computer.
Increased Density through Stacking
Emerging in the late 2020s, CFETs will stack the CMOS transistor pairs on top of each other, automatically doubling the density of chips. Estimates are that the first CFET chips will contain approximately 150 to 200 million transistors per square millimeter, up from the 100 million or so today.
In time, the 3D architecture is expected to stack entire circuits, not just CMOS transistor pairs. For example, layers of transistors combined with layers for memory, chip control, caches, CPU cores and an AI accelerator are expected. The source of power is also likely to come from the bottom of the chip rather than the top where it is today.
A Half Billion Transistors on a Pinhead!
Today, a chip can contain more than 100 million transistors per square millimeter, about the same area as the head of a pin. When 3D architecture like the layers example above is employed and fully matured for complete circuits, the number of transistors should triple, quadruple and even quintuple. That means a half billion transistors per square millimeter are possible within the next decade! Stay tuned! See Cerebras AI computer.