Term of the Moment
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Definition: active area
The active area is the transistor layer in a chip where all the switching takes place. Depending on transistor type, it is from five to 90 nanometers (nm) thick. In the future, 3D stacking of transistors will create thicker active areas because a chip will have multiple transistor layers (see CFET). See chip, half-adder and Boolean logic.
Entirely Magical
No man-made object is more incredible than the chip. Today's state-of-the-art CPUs and SoCs contain billions of transistors, many millions of which are simultaneously switching their state from on to off and off to on every second. In fact, so many transistors are changing at the same time that there can be quadrillions and quintillions of transistor state changes taking place every second. Think about that number... quadrillions and quintillions of changes every second for hours on end in digital perfection. See head of a pin, transistor and SoC.
A Digital Miracle
There Are Many Layers on a Chip
Entirely Magical
No man-made object is more incredible than the chip. Today's state-of-the-art CPUs and SoCs contain billions of transistors, many millions of which are simultaneously switching their state from on to off and off to on every second. In fact, so many transistors are changing at the same time that there can be quadrillions and quintillions of transistor state changes taking place every second. Think about that number... quadrillions and quintillions of changes every second for hours on end in digital perfection. See head of a pin, transistor and SoC.
When people look at a chip package like this, they see an object about the size of a cracker. However, inside the package, the chip may be larger or smaller than a postage stamp, but the active area on the chip is significantly thinner. The transistor layer combined with all the metal interconnection layers and the top power layer is 10,000 nanometers deep (nm) on average. A postage stamp is about 150,000 nm. See microcontroller and chip package.
Because all the transistors cannot connect to each other on a single plane, multiple "metal layers" are created to provide all the interconnections. Compare the roughly 10,000-nanometer thickness of the chip layers with a single human hair, which can be from 50,000 to 120,000 nanometers in diameter. See process technology.