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Redirected from: HBM2
Definition: high bandwidth memory
A high-speed interface for memory chips adopted by JEDEC in 2013. Used with GPUs designed for AI training and other high-performance applications, high bandwidth memory (HBM) uses a 3D stacked architecture of DRAM (dynamic RAM) modules.
A Much Wider Interface
The 4096-bit interface connecting HBM memory to the CPU or GPU is eight times wider than the 512 bits used for DDR and GDDR memory. This results in memory that is from 10 to 30 times faster than DDR. See Hybrid Memory Cube and GDDR.
For AI, HBM and DDR Work Together
DDR memory holds the program code as well as the data before GPU processing. HBM holds the data the GPU works on, which are the nodes and layers of the neural network. In fact, HBM resides on the same chip package as the GPU.
A Micron 24GB HBM3e Cube
HBM in a Superchip
A Much Wider Interface
The 4096-bit interface connecting HBM memory to the CPU or GPU is eight times wider than the 512 bits used for DDR and GDDR memory. This results in memory that is from 10 to 30 times faster than DDR. See Hybrid Memory Cube and GDDR.
For AI, HBM and DDR Work Together
DDR memory holds the program code as well as the data before GPU processing. HBM holds the data the GPU works on, which are the nodes and layers of the neural network. In fact, HBM resides on the same chip package as the GPU.
HBM modules are built in layers that must be perfectly aligned over each other. For example, HBM4 stacks 16 DDR layers, each holding 4GB for a total of 64GB. SK Hynix was first to ship HBM in 2013, but Micron became the leading supplier of HBM3 by 2026. (Image courtesy of Micron Technology, Inc.)
Data Layers x GB
Date of Rate =
Release (GB/s) Total GB Volts
HBM4 2026 1638 16x4=64 0.4
HBM3e 2023 1229 16x3=48 0.4
HBM3 2022 819 12x2=24 0.4
HBM2e 2019 461 12x2=25 1.2
HBM2 2016 307 8x1=8 1.2
HBM1 2013 128 4x1=4 1.2
NVIDIA's Superchip uses HBM memory for its built-in GPU. See NVIDIA Grace Hopper Superchip.